full feature peak reducing emi solution w182 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07151 rev. *a revised september 24, 2001 features cypress premis? family offering generates an emi optimized clocking signal at the output selectable output frequency range single 1.25% or 3.75% down or center spread output integrated loop filter components operates with a 3.3 or 5v supply low power cmos design available in 14-pin soic (small outline integrated circuit) key specifications supply voltages: ...........................................v dd = 3.3v5% or v dd = 5v10% frequency range: .............................. 8 mhz f in 28 mhz cycle to cycle jitter: ........................................ 300 ps (max.) selectable spread percentage: ....................1.25% or 3.75% output duty cycle: ............................... 40/60% (worst case) output rise and fall time: .................................. 5 ns (max.) table 1. modulation width selection ss% w182 output w182-5 output 0f in f out f in ? 1.25% f in + 0.625% f in ? 0.625% 1f in f out f in ? 3.75% f in + 1.875% f in ? 1.875% table 2. frequency range selection fs2 fs1 frequency range 00 8 mhz f in 10 mhz 01 10 mhz f in 15 mhz 10 15 mhz f in 18 mhz 11 18 mhz f in 28 mhz premis is a trademark of cypress semiconductor corporation. simplified block diagram pin configuration soic spread spectrum w182 (emi suppressed) 3.3v or 5.0v oscillator or spread spectrum w182 (emi suppressed) 3.3v or 5.0v xtal x1 x2 reference input input output output w182/w182-5 14 13 12 11 1 2 3 4 fs2 clkin or x1 nc or x2 gnd refout oe# sson# reset 5 6 7 8 9 10 vdd vdd clkout gnd ss% fs1
w182 document #: 38-07151 rev. *a page 2 of 9 pin definitions pin name pin no. pin type pin description clkout 8 o output modulated frequency : frequency modulated copy of the input clock (sson# asserted). refout 14 o non-modulated output: this pin provides a copy of the reference frequency. this output will not have the spread spectrum feature enabled regardless of the state of logic input sson#. clkin or x1 2 i crystal connection or external reference frequency input: this pin has dual functions. it may either be connected to an external crystal, or to an external reference clock. nc or x2 3 i crystal connection: input connection for an external crystal. if using an ex- ternal reference, this pin must be left unconnected. sson# 12 i spread spectrum control (active low): asserting this signal (active low) turns the internal modulation waveform on. this pin has an internal pull-down resistor. ss% 6 i modulation width selection: when spread spectrum feature is turned on, this pin is used to select the amount of variation and peak emi reduction that is desired on the output signal. this pin has an internal pull-up resistor. oe# 13 i output enable (active low): when this pin is held high, the output buffers are placed in a high-impedance mode.this pin has an internal pull-down re- sistor. reset 11 i modulation profile restart: a rising edge on this input restarts the modulation pattern at the beginning of its defined path. this pin has an internal pull-down resistor. fs1:2 7, 1 i frequency selection bit(s): these pins select the frequency range of oper- ation. refer to table 2 . these pins have internal pull-up resistors. vdd 9,10 p power connection: connected to 3.3v or 5v power supply. gnd 4,5 g ground connection: connect all ground pins to the common ground plane.
w182 document #: 38-07151 rev. *a page 3 of 9 overview the w182 product is one of a series of devices in the cypress premis family. the premis family incorporates the latest advances in pll spread spectrum frequency synthesizer tech- niques. by frequency modulating the output with a low-fre- quency carrier, peak emi is greatly reduced. use of this tech- nology allows systems to pass increasingly difficult emi testing without resorting to costly shielding or redesign. in a system, not only is emi reduced in the various clock lines, but also in all signals which are synchronized to the clock. therefore, the benefits of using this technology increase with the number of address and data lines in the system. the sim- plified block diagram shows a simple implementation. functional description the w182 uses a phase-locked loop (pll) to frequency modulate an input clock. the result is an output clock whose frequency is slowly swept over a narrow band near the input signal. the basic circuit topology is shown in figure 1 . the input reference signal is divided by q and fed to the phase detector. a signal from the vco is divided by p and fed back to the phase detector also. the pll will force the frequency of the vco output signal to change until the divided output signal and the divided reference signal match at the phase detector input. the output frequency is then equal to the ratio of p/q times the reference frequency. (note: for the w182 the output frequency is nominally equal to the input frequency.) the unique feature of the spread spectrum frequency timing generator is that a modulating waveform is superimposed at the input to the vco. this causes the vco output to be slowly swept across a predetermined frequency band. because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum pro- cess has little impact on system performance. frequency selection with ssftg in spread spectrum frequency timing generation, emi re- duction depends on the shape, modulation percentage, and frequency of the modulating waveform. while the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. using frequency select bits (fs2:1 pins), the frequency range can be set (see table 2 ). spreading percentage is set with pin ss% as shown in table 1 . a larger spreading percentage improves emi reduction. how- ever, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. for these reasons, spreading percentage options are provided. freq. phase modulating vco post clkout detector charge pump waveform dividers divider feedback divider pll gnd v dd q p clock input reference input (emi suppressed) figure 1. functional block diagram
w182 document #: 38-07151 rev. *a page 4 of 9 spread spectrum frequency timing generation the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 2 . as shown in figure 2 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 3 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. figure 3 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. ssftg typical clock frequency span (mhz) amplitude (db) spread spectrum enabled emi reduction spread spectrum non- frequency span (mhz) down spread amplitude (db) center spread figure 2. clock harmonic with and without sscg modulation frequency domain representation max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 3. typical modulation profile
w182 document #: 38-07151 rev. *a page 5 of 9 absolute maximum ratings [1] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : 0 c < t a < 70 c, v dd = 3.3v 5% parameter description test condition min. typ. max. unit i dd supply current 18 32 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.8 v v ih input high voltage 2.4 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 2 ? 50 a i ih input high current note 2 50 a i ol output low current @ 0.4v, v dd = 3.3v 15 ma i oh output high current @ 2.4v, v dd = 3.3v 15 ma c i input capacitance 7pf r p input pull-up resistor 500 k ? z out clock output impedance 25 ? note: 1. single power supply: the voltage on any input or i/o pin cannot exceed the power pin during power up. 2. inputs fs2:1 have a pull-up resistor; input sson# has a pull-down resistor.
w182 document #: 38-07151 rev. *a page 6 of 9 dc electrical characteristics: 0 c < t a < 70 c, v dd = 5v 10% parameter description test condition min. typ. max. unit i dd supply current 30 50 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.15v dd v v ih input high voltage 0.7v dd v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 3 ? 50 a i ih input high current note 3 50 a i ol output low current @ 0.4v, v dd = 5v 24 ma i oh output high current @ 2.4v, v dd = 5v 24 ma c i input capacitance 7pf r p input pull-up resistor 500 k ? z out clock output impedance 25 ? ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 5% or 5v10% symbol parameter test condition min. typ. max. unit f in input frequency input clock 8 28 mhz f out output frequency spread off 8 28 mhz t r output rise time 15-pf load, 0.8v ? 2.4v 2 5 ns t f output fall time 15-pf load, 2.4 ? 0.8v 2 5 ns t od output duty cycle 15-pf load 40 60 % t id input duty cycle 40 60 % t jcyc jitter, cycle-to-cycle 250 300 ps harmonic reduction f out = 20 mhz, third harmonic measured, reference board, 15-pf load 8db note: 3. inputs fs1:2 have a pull-up resistor; input sson# has a pull-down resistor.
w182 document #: 38-07151 rev. *a page 7 of 9 application information recommended circuit configuration for optimum performance in system applications the power supply decoupling scheme shown in figure 4 should be used. v dd decoupling is important to both reduce phase jitter and emi radiation. the 0.1- f decoupling capacitor should be placed as close to the v dd pin as possible, otherwise the in- creased trace inductance will negate its decoupling capability. the 10- f decoupling capacitor shown should be a tantalum type. for further emi protection, the v dd connection can be made via a ferrite bead, as shown. recommended board layout figure 5 shows a recommended a 2-layer board layout. figure 4. recommended circuit configuration gnd w182 14 13 12 11 1 2 3 4 c1 fb c2 3.3v or 5v system supply 10 f tantalum 0.1 f clock output r1 10 9 8 5 6 7 xtal connection or nc xtal connection or reference input c3 0.1 f clock output high-frequency supply decoupling capacitor (0.1- f recommended). common supply low frequency decoupling capacitor (10- f tantalum recommended). fb ferrite bead c1, c3 = c2 = match value to line impedance r1 = = r1 c1 c2 g g fb = via to gnd plane g nc g (3.3v or 5v) c3 g power supply input xtal connection or reference input g xtal connection or figure 5. recommended board layout (2-layer board) ordering information ordering code package name package type w182 w182-5 g 14-pin plastic soic (150-mil)
w182 document #: 38-07151 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 14-pin small outline integrated circuit (soic, 150-mil)
w182 document #: 38-07151 rev. *a page 9 of 9 document title: w182 full feature peak reducing emi solution document number: 38-07151 rev. ecn no. issue date orig. of change description of change ** 110261 12/15/01 szv change from spec number: 38-00789 to 38-07151 *a 122686 12/27/02 rbi added power up requirements to maximum ratings information.
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